With the improving of the available technologies and the demand for ever increasing precision, it is of ever increasing importance to realize circuits wherein the precision with which a certain factor, parameter or entity is controlled or delivered be constant. This should be so despite the varying of numerous others parameters such as temperature, supply voltage, bias current, etc.
Operational amplifiers and more specifically error amplifiers or differential comparators are truly building blocks of complex systems for analog processing of signals. Differential amplifiers, if considered, for example, in their function as error amplifiers, are intuitively the kind of circuits for which a great precision is a fundamental requirement. Therefore hereinafter reference will be made simply by way of an example to a differential comparator with null threshold voltage, also referred to as a zero cross comparator, as representing one of the most typical differential amplifier circuits requiring a high precision despite varying operating conditions, such as temperature, supply voltage, bias current, etc.
FIGS. 1 and 2 show the two stages or more precisely the input part and the output part, respectively, of a common zero comparator. The zero comparator has a substantially null threshold, and is integrated in MOS technology. It employs an output NAND gate comprising transistors M26, M27, M33 and M47, which are enabled or disabled by way of a logic signal en.
The input stage of FIG. 1 is not directly involved or pertinent to the subject matter of the present invention or to the physical implementation of the circuit components that realize the circuit of the invention, however it is reproduced for the sake of completeness of illustration. The input stage of FIG. 1 has a quite common circuit configuration according to an implementation with MOS transistors of complementary types. Accordingly, the circuit can function from ground up to the supply voltage.
FIG. 2 depicts the output stage of the comparator, that is, the part that is directly involved in implementing the circuit of the present invention. Referring to FIG. 1, the two lines diffA and diffB represent the two differential output lines of the input stage of complementary symmetry. Therefore, the two currents Ia1 and Ib1 are equal when the two inputs (+) and (-) of the comparator are at the same voltage.
Generally, by assuming that Ia1=Ib1=I and considering the output circuit block of FIG. 2, the current Ia2 and Ib2 are obtained by the difference between the drain currents of the transistors M19 and M64 and the output currents of the input circuit Ial and Ib1, which according to the initial assumption, are both equal to I. The transistors M19 and M64 provide two generators of a constant bias current for the two branches of the current mirror circuit provided by M5 and M6, which includes also a level shifting circuit. A constant bias current is provided because M19 and M64 provide the strong sides of a current mirror having as its reference the biasing diode M20 of the input circuit.
To achieve the maximum voltage swing without wasting current it may be assumed normally that I.sub.dM19 =I.sub.dM64 =Ia1+Ib1=2I. Therefore in a balanced condition of the inputs: Ia2=Ib2=I. These currents flow toward a respective active load, represented by the transistors M5 and M6 of a current mirror circuit that drives a load transistor M71. The potential level of the load transistor M71 is referred to another transistor M69 connected between the ground node and the output node of the output stage.
If, as in the above described example, the transistor M71 has a gate length double that of the transistors M5 and M6, with identical currents, it will deliver Ic=I/2. To match the circuit it will be necessary to cause the transistor M65 to generate a current Ica=I/2. For this reason, its width (w) must be equal to half the width of the biasing reference diode M20.
It has been observed that in a classical circuit as the one depicted in FIGS. 1 and 2, the maximum band of the circuit, from which the speed of the comparator depends, is limited by the output band of the active load. Therefore, the output band is limited by the band available on the drain node of M6, to which the gate M71 is coupled.
To increase the useful band, the sizes of these transistors may be reduced. Once the minimum size permitted by the fabrication technology is reached, the only way to increase the band is to increase the signal currents Ia2 and Ib2 of the output stage. In fact, an increase of just the bias currents of the two branches for the currents I.sub.dM19 and I.sub.dM64, does not have any effect on the band because the input signal acts by way of Ia1 and Ib1, Therefore, to increase the band it is necessary to increase Ia1=Ib1=I and by consequence also I.sub.dM19 =I.sub.dM64 =Ia1+Ib1=2I, to maintain unchanged the dynamic characteristics of the circuit.
On the other hand, through the biasing diode M20, the circuit is affected by the body effect of the transistors M21 and M3 that generate the bias currents of the input circuit. These currents increase upon an increase of the supply voltage that increases the Vds of the above-mentioned MOS transistors M21 and M3.
In contrast, the transistors M19 and M64 are not so affected because their drains are fixed at the voltage imposed by the voltage shifting stage provided by M68 and M67. On the other hand, it would be counterproductive to remove such a voltage shifting stage because another source of error would be introduced in the mirrored currents.
Therefore, the transistor M69 mirrors M20 directly without being affected by the variation of the currents I.sub.dM21 and I.sub.dM3. Moreover, it is subjected to a different Vds voltage than that of the respective transistors, and, therefore, causes an error because of a different body effect. As a consequence, upon the varying of the input voltage and even of the operating point of the inputs (+) and (-), the offset of the comparator shifts appreciably giving rise to threshold error.